1. Field of the Invention
The present invention relates to a stacked die structure and, more particularly, to a stacked die structure with an underlying copper-topped die, and a method of forming the stacked die structure.
2. Description of the Related Art
A copper-topped die is an integrated circuit chip that utilizes copper traces in lieu of aluminum traces to form the top layer of the metal interconnect structure. By using copper traces in place of aluminum traces, the resistance of the top layer of the metal interconnect structure can be substantially reduced.
FIGS. 1A-1B show views that illustrate a prior-art copper-topped die 100. FIG. 1A shows a plan view, while FIG. 1B shows a cross-sectional view taken along line 1B-1B of FIG. 1A. As shown in FIGS. 1A-1B, copper-topped die 100 includes a substrate material 110, and a number of semiconductor devices that are formed in and on substrate material 110.
The semiconductor devices, which include resistors, transistors, capacitors, diodes, and similar devices, have a number of conductive contact regions 112, such as the ends of a resistor and the terminals of a transistor, that are formed in substrate material 110. Each conductive contact region 112 has a dopant concentration that is greater than the dopant concentration of substrate material 110.
Copper-topped die 100 also includes a multi-layered metal interconnect structure 114 that touches semiconductor material 110 and the semiconductor devices (e.g., the conductive contact regions 112) to electrically connect the semiconductor devices together to realize an electrical circuit.
Metal interconnect structure 114 includes a number of contacts 114C that touch the conductive contact regions 112 (either directly or via silicide). Metal interconnect structure 114 also includes a number of metal-1 traces 114-M1 that are connected to the contacts 114C, a number of metal-2 traces 114-M2, a number of metal-3 traces 114-M3, and a number of metal-4 traces 114-M4. In the present example, the metal-1 traces 114-M1, the metal-2 traces 114-M2, the metal-3 traces 114-M3, and the metal-4 traces 114-M4 are implemented with aluminum or an aluminum alloy.
In addition, metal interconnect structure 114 includes a number of inter-metal vias 114V that connect the metal-1 traces 114-M1 and the metal-2 114-M2 traces together, the metal-2 traces 114-M2 and the metal-3 114-M3 traces together, and the metal-3 traces 114-M3 and the metal-4 114-M4 traces together.
Metal interconnect structure 114 further includes an insulation region 114I that touches semiconductor substrate 110, the semiconductor devices (e.g., the conductive contacts 112), the contacts 114C, the metal-1 traces 114-M1, the metal-2 traces 114-M2, the metal-3 traces 114-M3, the metal-4 traces 114-M4, and the inter-metal vias 114V. In the present example, insulation region 114I includes a region of oxide 114L and an overlying passivation layer 114U. Passivation layer 114U, which has a top surface 114S, can be implemented with, for example, oxide, nitride, or a combination of oxide and nitride.
In addition, metal interconnect structure 114 includes a number of copper traces 114CL, including copper lines 114T and copper pads 114P, that touch the top surface of passivation layer 114U, and also extend through passivation layer 114U as necessary to make electrical connections with selected regions on the top surfaces of the aluminum metal-4 traces 114-M4. Each copper trace 114CL typically includes a copper layer 114G and an underlying seed layer 114H. Seed layer 114H typically includes a layer of titanium (e.g., 300 Å thick) and an overlying layer of copper (e.g., 3000 Å thick). The titanium layer enhances the adhesion between the underlying aluminum metal-4 traces 114-M4 and the overlying layer of copper.
Further, metal interconnect structure 114 includes a number of conductive covers 114AC that touch the top surfaces of the copper traces 114CL to provide wire bonding surfaces for the copper pads 114P. Each conductive cover 114AC typically includes an overlying layer 114Q, such as aluminum, aluminum-copper (e.g., 0.5% copper), or gold, and an underlying barrier/adhesion enhancing layer 114R, such as titanium, that provides a metal barrier and enhances the adhesion of layer 114Q to the underlying copper in the copper traces 114CL. Wire bond lines 116 can then be attached to the conductive covers 114AC that lie over the copper pads 114P. Thus, with copper-topped die 100, the conductive covers 114AC and the underlying copper lines 114T and copper pads 114P are exposed.
One well-known approach to effectively increasing the total silicon surface area of a die, and thereby increasing the number of semiconductor devices that can be formed on the die, without increasing the printed circuit board (PCB) footprint required by the die is to vertically stack one die on top of another.
FIG. 2A shows a cross-sectional view that illustrates a prior-art stacked die structure 200. As shown in FIG. 2A, stacked die structure 200 includes a lower die 210, and an upper die 212 that is attached to the top surface of lower die 210. Lower die 210 is similar to copper-topped die 100 and, as a result, utilizes the same reference numerals to designate the structures which are common to both die.
Lower die 210 differs from die 100 in that lower die 210 includes a metal interconnect structure 214 in lieu of metal interconnect structure 114. Metal interconnect structure 214 is identical to metal interconnect structure 114 except that: (1) the aluminum metal-4 traces 114-M4, which have both aluminum lines 120T and aluminum pads 120P, form the top metal layer (which provides an external electrical connection point); (2) passivation layer 114U includes a number of openings 216 that extend through passivation layer 114U to expose the aluminum pads 120P; (3) the copper traces 114CL are absent; and (4) the conductive covers 114AC are absent.
In addition, upper die 212 is similar to lower die 210. Upper die 212 differs from lower die 210 in that upper die 212 has a smaller footprint and can realize a different electrical circuit than lower die 210. As a result, upper die 212 utilizes the same reference numerals as lower die 210 to designate the structures which are common to both dice. Wire bond lines 218 can then be used to connect the aluminum pads 120P on upper die 212 to the aluminum pads 120P on lower die 210.
As a result of the structure of lower die 210, which is topped by passivation layer 114U, upper die 212 can be directly attached to the top surface of lower die 210 (by way of an adhesive such as glue) because the bottom surface of upper die 212 (which is a conductive substrate) only touches non-conductive passivation layer 114U of lower die 210.
One problem with copper-topped die 100, however, is that copper-topped die 100 can not be used as an underlying die in a stacked die structure. This is because if an upper die were directly attached to the top surface of copper-topped die 100, then the conductive covers 114AC will directly contact, and be shorted out by, the bottom surface (which is a conductive substrate) of upper die 212.
One approach to this problem is to attach an insulting sheet of material to the bottom side of the upper die. FIG. 2B shows a cross-sectional view that illustrates a prior-art stacked die structure 250 that utilizes an insulating sheet of material. As shown in FIG. 2B, stacked die structure 250 includes a lower die 252 and an upper die 254. Lower die 252 is identical to copper-topped die 100 and, as a result, utilizes the same reference numerals to designate the structures which are common to both dice. Upper die 254 is identical to upper die 212 and, as a result, utilizes the same reference numerals to designate the structures which are common to both dice.
In addition, stacked die structure 250 includes an insulting sheet 256 that physically connects die 252 to die 254, and a wire bonding line 258 that electrically connects die 252 to die 254. Insulating sheet 256 is adhesively attached to the top surfaces of the conductive covers 114AC of lower die 252, and to the bottom surface of upper die 254.
Although insulating sheet 256 prevents the conductive covers 114AC of lower die 252 from being shorted out by the conductive substrate of upper die 254, insulating sheet 256 provides poor mechanical stability due to the limited number of places where insulating sheet 256 is attached to lower die 252. As a result, there is a need for a stacked die structure that can utilize a copper-topped lower die.